#if defined(TSINGMA_MX) || defined(TSINGMA_GX) || defined(ARCTIC)

#include "sal_types.h"
#include "sal.h"
#include "sys_usw_acl.h"
#include "sys_usw_acl_extract.h"

extern sys_acl_master_t* p_usw_acl_master[CTC_MAX_LOCAL_CHIP_NUM_PP];

STATIC int32
_sys_tmm_acl_ingress_field_cfg_db_init(uint8 lchip)
{
    sys_acl_field_flags_bmp_t field_flags;
    sys_acl_kfield_cfg_info_db_t *db = NULL;
    SYS_ACL_KFIELD_CFG_DECL;

    STS_ACL_FUNC_ENTER(lchip);

    SYS_ACL_ALLOC(p_usw_acl_master[lchip]->kgn_field_cfg_info_db,
                sizeof(sys_acl_kfield_cfg_info_db_t));




    db = p_usw_acl_master[lchip]->kgn_field_cfg_info_db;
    sal_memset(&field_flags, 0, sizeof(sys_acl_field_flags_bmp_t));



  //32 ------------------------------------------
#if 0
    CBit fs32Pbm7                         ; // 32
    CBit fs32Pbm6                         ; // 32
    CBit fs32Pbm5                         ; // 32
    CBit fs32Pbm4                         ; // 32
    CBit fs32Pbm3                         ; // 32
    CBit fs32Pbm2                         ; // 32
    CBit fs32Pbm1                         ; // 32
    CBit fs32Pbm0                         ; // 32
    CBit fs32Udf3                         ; // 32
    CBit fs32Udf2                         ; // 32
    CBit fs32Udf1                         ; // 32
    CBit fs32Udf0                         ; // 32
    CBit fs32MergeData0                   ; // 32
    CBit fs32MergeData1                   ; // 32
    CBit fs32IntData0                     ; // 32
    CBit fs32IntData1                     ; // 32
    CBit fs32IntData2                     ; // 32
    CBit fs32V6B0To3                      ; // 32
    CBit fs32SIp3                         ; // 32
    CBit fs32SIp2                         ; // 32
    CBit fs32SIp1                         ; // 32
    CBit fs32SIp0                         ; // 32
    CBit fs32DIp3                         ; // 32
    CBit fs32DIp2                         ; // 32
    CBit fs32DIp1                         ; // 32
    CBit fs32DIp0                         ; // 32
    CBit fs32SMac                         ; // 32
    CBit fs32DMac                         ; // 32
#endif

    //fs32DMac
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 0, 0, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 0, 0, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAC_DA, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 0, 0, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 0, 0, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TARGET_MAC, field_flags);

    //fs32SMac
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 1, 32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 1, 16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAC_SA, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 1, 32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 1, 16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SENDER_MAC, field_flags);

    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 64, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_DA, field_flags);

    //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 192, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_SA, field_flags);

    //fs32Pbm0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 20, 20*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 12, 12*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_PORT_BITMAP_MODE0, field_flags);

    //fs32Pbm1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 20, 20*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 21, 21*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E4, 12, 12*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_PORT_BITMAP_MODE1, field_flags);

    //fs32Pbm2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 20, 20*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 21, 21*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 22, 22*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E32, 23, 23*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(4, SYS_ACL_KEXT_SECTION_L1E4, 12, 12*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_PORT_BITMAP_MODE2, field_flags);

    //fs32Pbm7-0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 20, 20*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 21, 21*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 22, 22*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E32, 23, 23*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(4, SYS_ACL_KEXT_SECTION_L1E32, 24, 24*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(5, SYS_ACL_KEXT_SECTION_L1E32, 25, 25*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(6, SYS_ACL_KEXT_SECTION_L1E32, 26, 26*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(7, SYS_ACL_KEXT_SECTION_L1E32, 27, 27*32, 32);
    if DRV_FROM_AT(lchip)
    {
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(8, SYS_ACL_KEXT_SECTION_L1E4, 12, 12*4, 4);
    }
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_PORT_BITMAP_MODE3, field_flags);


    //fs32DIp0-3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 64, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 3, 96, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 4, 128, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E32, 5, 160, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPV6_DA, field_flags);

    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 64, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_DA_CHUNK0, field_flags);
    //fs32DIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 3, 96, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_DA_CHUNK1, field_flags);
    //fs32DIp2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 4, 128, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_DA_CHUNK2, field_flags);
    //fs32DIp3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 5, 160, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_DA_CHUNK3, field_flags);

    //fs32SIp0-3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 192, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 7, 224, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 8, 256, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E32, 9, 288, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPV6_SA, field_flags);

    //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 192, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_SA_CHUNK0, field_flags);
    //fs32SIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 7, 224, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_SA_CHUNK1, field_flags);
    //fs32SIp2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 8, 256, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_SA_CHUNK2, field_flags);
    //fs32SIp3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 9, 288, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_SA_CHUNK3, field_flags);

    /*ARP*/
    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_TARGET_IP, field_flags);

    //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_SENDER_IP, field_flags);

    //fs32DIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 3, 3*32, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_HARDWARE_TYPE, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 3, 3*32+16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_PROTOCOL_ADDLEN, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 3, 3*32+24, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_HARDWARE_ADDLEN, field_flags);

    /*MPLS*/
    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_TTL0, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 8, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_SBIT0, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 9, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_EXP0, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 12, 20);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL0, field_flags);


    //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_TTL1, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 8, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_SBIT1, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 9, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_EXP1, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 12, 20);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL1, field_flags);

    //fs32SIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 7, 7*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL3, field_flags);

    //fs32DIp2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 4, 4*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL4, field_flags);

    //fs32SIp2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 8, 8*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL5, field_flags);

    //fs32DIp3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 5, 5*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL6, field_flags);

    //fs32SIp3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 9, 9*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL7, field_flags);

    /*SLOW PROTOCOL*/
    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SLOW_PROTOCOL_CODE, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 8, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SLOW_PROTOCOL_FLAGS, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 24, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SLOW_PROTOCOL_SUB_TYPE, field_flags);

    /*PTP*/
    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 16, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PTP_VERSION, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 24, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PTP_MESSAGE_TYPE, field_flags);


    /*EthOam*/
    //fs32DIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ETHER_OAM_OP_CODE, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 24, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ETHER_OAM_VERSION, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 29, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ETHER_OAM_LEVEL, field_flags);


    /*FCOE*/
    //fs32DIp0     //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 24);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FCOE_DST_FCID, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 24);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FCOE_SRC_FCID, field_flags);


   /*TRILL*/
    //fs32DIp0     //fs32SIp0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_EGRESS_NICKNAME, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 16, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TRILL_TTL, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 27, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TRILL_MULTICAST, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 30, 2);//27
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TRILL_VERSION, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INGRESS_NICKNAME, field_flags);


    /*SATPDU*/
    //fs32DIp0     //fs32SIp0     //fs32DIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 8, 24);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SATPDU_MEF_OUI, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 24, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SATPDU_OUI_SUB_TYPE, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 7, 7*32 + 24, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 3, 3*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 24);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SATPDU_PDU_BYTE, field_flags);


    /*DOT1AE*/
    //fs32DIp0     //fs32SIp0  //fs32DIp1     //fs32SIp1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_AN, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_CBIT, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 3, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_EBIT, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 4, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_SCB, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 5, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_SC, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 6, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_ES, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 7, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_VER, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_SL, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_PN, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 3, 3*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E32, 7, 7*32, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DOT1AE_SCI, field_flags);


    //fs32V6B0To3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 10, 10*32, 20);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPV6_FLOW_LABEL, field_flags);


    //fs32IntData2 11
    //fs32IntData1 12
    //fs32IntData0 13



    //fs32MergeData1 14
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 14, 14*32, 24);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VXLAN_RSV1, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 14, 14*32 + 24, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VXLAN_RSV2, field_flags);

    //fs32MergeData0 15

#if 0
    CTC_FIELD_KEY_FROM_CF,                 /**< [TMM] From CF(stacing)ports */
    CTC_FIELD_KEY_CF_DST_GPORT,            /**< [TMM] CFlexHeader dest port */
    CTC_FIELD_KEY_CF_SRC_GPORT,            /**< [TMM] CFlexHeader src port */
    CTC_FIELD_KEY_CF_LOGIC_SRC_PORT,       /**< [TMM] CFlexHeader logic src port */
    CTC_FIELD_KEY_CF_PRIORITY,             /**< [TMM] CFlexHeader priority */
    CTC_FIELD_KEY_CF_SRC_CID,              /**< [TMM] CFlexHeader source cid */
    CTC_FIELD_KEY_CF_MIRROR_PKT,           /**< [TMM] CFlexHeader mirror packet*/

 IpeToAclCFlexInfo.cflexHdrData(90,0) = (tempFromLag,tempPriority(3,0),cflexDestMap(21,0),tempIsSpanPkt,tempLearningFid(14,0),cflexSourcePort(15,0),tempLogicSrcPort(15,0),tempI2eSrcCid(15,0));
#endif

    //CF Header, share fs32Udf0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_SRC_CID, field_flags);
    //CF Header, share fs32Udf0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_LOGIC_SRC_PORT, field_flags);
    //CF Header, share fs32Udf1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_SRC_GPORT, field_flags);
    //CF Header, share fs32Udf1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32+16, 15);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_FID, field_flags);
    //CF Header, share fs32Udf1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32+31, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_MIRROR_PKT, field_flags);
    //CF Header, share fs32Udf2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 18, 18*32, 22);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_DST_GPORT, field_flags);
    //CF Header, share fs32Udf2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 18, 18*32+22, 4);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_PRIORITY, field_flags);

    if (DRV_FROM_AT(lchip))
    {
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32 + 24, 8);    /*fs32NshHeaderData0*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_NH, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32 + 8, 8);    /*fs32NshHeaderData0*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_RT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32, 8);    /*fs32NshHeaderData0*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_SL, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32 + 24, 8);    /*fs32NshHeaderData1*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_LE, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32 + 16, 8);    /*fs32NshHeaderData1*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_FLAG, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32, 16);    /*fs32NshHeaderData1*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_TAG, field_flags);

        //fs32NshHeaderData0.FlowId
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32 + 12, 20);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_FLOW_ID, field_flags);
        //fs32NshHeaderData0.LFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32+10, 2);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_L_FLAG, field_flags);
        //fs32NshHeaderData0.DFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32+9, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_D_FLAG, field_flags);

        //fs32NshHeaderData1.FlowId
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32 + 12, 20);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_IM_FLOW_ID, field_flags);
        //fs32NshHeaderData1.LFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32+10, 2);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_IM_L_FLAG, field_flags);
        //fs32NshHeaderData1.DFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32+9, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IPV6_IM_D_FLAG, field_flags);
    }
    else
    {
        //fs32UdfA2
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+8, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_NH, field_flags);
        //fs32UdfA0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_RT, field_flags);
        //fs32UdfA0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+16, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_SL, field_flags);
        //fs32UdfA1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32+16, 16);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_TAG, field_flags);
        //fs32UdfA1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32+8, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_LE, field_flags);
        //fs32UdfA1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRV6_SRH_FLAG, field_flags);
    }

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    //fs8UdfAProfileId
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 8, 8*8, 8);
    //fs2UdfAProfileIdHigh
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 27, 27*2, 2);
    //fs8UdfAValid
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E8, 9, 9*8, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_SRH_COMMON_HDR, field_flags);

    //fs32UdfA0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK0, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK1, field_flags);

    //fs32UdfA1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK2, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 17, 17*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK3, field_flags);

    //fs32UdfA2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 18, 18*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK4, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 18, 18*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK5, field_flags);

    //fs32UdfA3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 19, 19*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK6, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 19, 19*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_CHUNK7, field_flags);


    //CF Header, share fs32UdfB0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 30, 30*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_SRC_CID, field_flags);
    //CF Header, share fs32UdfB0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 30, 30*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_LOGIC_SRC_PORT, field_flags);
    //CF Header, share fs32UdfB1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 31, 31*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_SRC_GPORT, field_flags);
    //CF Header, share fs32UdfB1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 31, 31*32+16, 15);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_FID, field_flags);
    //CF Header, share fs32UdfB1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 31, 31*32+31, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_MIRROR_PKT, field_flags);
    //CF Header, share fs32UdfB2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 32, 32*32, 22);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_DST_GPORT, field_flags);
    //CF Header, share fs32UdfB2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 32, 32*32+22, 4);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_PRIORITY, field_flags);

    //fs32UdfB0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 30, 30*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK0, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 30, 30*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK1, field_flags);

    //fs32UdfB1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 31, 31*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK2, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 31, 31*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK3, field_flags);

    //fs32UdfB2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 32, 32*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK4, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 32, 32*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK5, field_flags);

    //fs32UdfB3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 33, 33*32, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK6, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 33, 33*32+16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_CHUNK7, field_flags);

    //fs32MplsControlWord
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 29, 29*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_CW, field_flags);

    //fs32MplsForwardingLabel
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 28, 28*32, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_FWD_TTL, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 28, 28*32 + 8, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_FWD_SBIT, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 28, 28*32 + 9, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_FWD_EXP, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 28, 28*32 + 12, 20);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_FWD_LABEL, field_flags);

    if (DRV_FROM_AT(lchip))
    {
         //fs32IntData2
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_INSTRUCTION, field_flags);

        //fs32IntData1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_REMAIN_HOP_CNT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+8, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_HOP_ML, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+23, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_MBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+24, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_EBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+28, 4);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_VER, field_flags);

        //fs32IntData0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+8, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_LEN, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_TYPE, field_flags);

    }
    else
    {
        //fs32IntData2
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_INSTRUCTION, field_flags);

        //fs32IntData1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_REMAIN_HOP_CNT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+8, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_HOP_ML, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+23, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_MBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+24, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_EBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32+28, 4);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_VER, field_flags);

        //fs32IntData0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+8, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_LEN, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_TYPE, field_flags);
    }

    if (DRV_FROM_AT(lchip))
    {
         //fs32IntData2
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+16, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_REMAIN_HOP_CNT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_HOP_ML, field_flags);

        //fs32IntData1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32, 32);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_INSTRUCTION, field_flags);

        //fs32IntData0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_VER, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+16, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_TYPE, field_flags);
    }
    else
    {
        //fs32IntData2
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+16, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_REMAIN_HOP_CNT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 11, 11*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_HOP_ML, field_flags);

        //fs32IntData1
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 12, 12*32, 32);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_INSTRUCTION, field_flags);

        //fs32IntData0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+24, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_VER, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 13, 13*32+16, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_INT_TYPE, field_flags);
    }


    //fs32XPIData0.FlowId
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 35, 35*32, 20);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XD_IM_FLOW_ID, field_flags);
    //fs32XPIData1.Lflag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 35, 35*32+22, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XD_IM_L_FLAG, field_flags);
    //fs32XPIData1.Dflag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 35, 35*32+21, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XD_IM_D_FLAG, field_flags);
    //fs32XPIData1.SRCDflag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 35, 35*32+27, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XD_IM_SRC_D_FLAG, field_flags);

    //fs32XPIData0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 35, 35*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_DW0, field_flags);
    //fs32XPIData1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 36, 36*32, 32);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_DW1, field_flags);

    //fs16XPIData0 
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 31, 31*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_W0, field_flags);
    //fs16XPIData1 
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 32, 32*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_W1, field_flags);
    //fs16XPIData2 
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 33, 33*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_W2, field_flags);
    //fs16XPIData3 
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 34, 34*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_W3, field_flags);

    //fs8XPIData0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 14, 14*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_B0, field_flags);
    //fs8XPIData1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 15, 15*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_B0+1, field_flags);
    //fs8XPIData2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 16, 16*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_B0+2, field_flags);
    //fs8XPIData3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 17, 17*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_XDATA_B3, field_flags);

  //fs32CflexHdrDataExt0
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 37, 37*32, 32);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_DW0, field_flags);
  //fs32CflexHdrDataExt1
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 38, 38*32, 32);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_DW1, field_flags);
  //fs16CflexHdrDataExt0 
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 31, 35*16, 16);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_W0, field_flags);
  //fs16CflexHdrDataExt1 
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 32, 36*16, 16);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_W1, field_flags);
  //fs8CflexHdrDataExt1
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 18, 18*8, 8);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_B0, field_flags);
  //fs8CflexHdrDataExt2
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 19, 19*8, 8);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_B1, field_flags);
  //fs8CflexHdrDataExt3
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 20, 20*8, 8);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_B2, field_flags);
  //fs8CflexHdrDataExt4
  SYS_ACL_KFIELD_CFG_INIT(lchip);
  SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 21, 21*8, 8);
  SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_XDATA_B3, field_flags);

  //16 ------------------------------------------
#if 0

    CBit fs16CategoryIdA                  ; // 16
    CBit fs16CategoryIdB                  ; // 16
    CBit fs16CategoryIdC                  ; // 16
    CBit fs16CategoryIdD                  ; // 16
    CBit fs16L2ExtField0                  ; // 16 new
    CBit fs16L2ExtField1                  ; // 16 new
    CBit fs16VsiId                        ; // 16 new
    CBit fs16MetaData                     ; // 16
    CBit fs16AuxFlexField1                ; // 16
    CBit fs16AuxFlexField0                ; // 16
    CBit fs16NextHopInfoL                 ; // 16
    CBit fs16DestMapL                     ; // 16
    CBit fs16SrcInfo1                     ; // 16
    CBit fs16SrcInfo0                     ; // 16
    CBit fs16RangeCheck                   ; // 16
    CBit fs16L3InterfaceId                ; // 16
    CBit fs16PiInnerVtag                  ; // 16
    CBit fs16PiOuterVtag                  ; // 16
    CBit fs16L4ExtField5                  ; // 16
    CBit fs16L4ExtField4                  ; // 16
    CBit fs16L4ExtField3                  ; // 16
    CBit fs16L4ExtField2                  ; // 16
    CBit fs16L4ExtField1                  ; // 16
    CBit fs16L4ExtField0                  ; // 16
    CBit fs16L4Bytes2To3                  ; // 16
    CBit fs16L4Bytes0To1                  ; // 16
    CBit fs16EtherType                    ; // 16
    CBit fs16PrInnerVtag                  ; // 16
    CBit fs16PrOuterVtag                  ; // 16
    CBit fs16SMac                         ; // 16
    CBit fs16DMac                         ; // 16

#endif


#if 0 //fs16DMac
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 0, 0, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAC_DA, field_flags);
#endif

#if 0 //fs16SMac
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 0, 16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAC_SA, field_flags);
#endif

    //fs16PrOuterVtag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 2, 32, 12);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SVLAN_ID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 2, 44, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STAG_CFI, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 2, 45, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STAG_COS, field_flags);

    //fs16PrInnerVtag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 3, 48, 12);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CVLAN_ID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 3, 60, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CTAG_CFI, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 3, 61, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CTAG_COS, field_flags);

    //fs16EtherType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 4, 4*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_FULL_ETHER_TYPE, field_flags);

    //fs16L4Bytes0To1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_SRC_PORT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16 + 8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ICMP_TYPE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ICMP_CODE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16 + 8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IGMP_TYPE, field_flags);

    //fs16L4Bytes2To3
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_DST_PORT, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_VNI_SHARE, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_L4_DP_SHARE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_VNI_SHARE, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_L4_SP_SHARE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 8);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_VNI_SHARE, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_VN_ID_SHARE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16 + 8, 8);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_VNI_SHARE, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_VXLAN_FLAGS_SHARE, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VN_ID, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16 + 8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VXLAN_FLAGS, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GRE_KEY, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16+8, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NVGRE_KEY, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GRE_FLAGS, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GRE_PROTOCOL_TYPE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_OP_CODE, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_PROTOCOL_TYPE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_TTL2, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16 + 8, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_SBIT2, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16 + 9, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_EXP2, field_flags);
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 5, 5*16 + 12, 4);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 6, 6*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MPLS_LABEL2, field_flags);


    //CBit fs16L4ExtField0 7


    //fs16L4ExtField1 8
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 8, 8*16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_OP_CODE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 8, 8*16 + 8, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_VERSION, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 8, 8*16 + 13, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_LEVEL, field_flags);


    //CBit fs16L4ExtField2 9
    //CBit fs16L4ExtField3 10
    //CBit fs16L4ExtField4 11
    //CBit fs16L4ExtField5 12


    //fs16PiOuterVtag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 13, 13*16, 12);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_SVLAN_ID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 13, 13*16+12, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_SVLAN_CFI, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 13, 13*16+13, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_SVLAN_COS, field_flags);

    //fs16PiInnerVtag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 14, 14*16, 12);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_CVLAN_ID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 14, 14*16+12, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_CVLAN_CFI, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 14, 14*16+13, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_CVLAN_COS, field_flags);

    //fs16L3InterfaceId
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 15, 15*16, 13);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INTERFACE_ID, field_flags);

    //fs16RangeCheck
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_RANGE_CHECK, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SVLAN_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CVLAN_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_PKT_LEN_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_SRC_PORT_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_DST_PORT_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_UDF_RANGE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SUDF_RANGE, field_flags);

    //SYS_ACL_KFIELD_CFG_INIT(lchip);
    //SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 16, 16*16, 13);
    //SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INTERFACE_ID, field_flags);

    //fs16SrcInfo0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 24, 24*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_GPORT_SHARE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 24, 24*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LOGIC_PORT_SHARE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 24, 24*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_METADATA, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GEM_PORT, field_flags);
#if 0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16 + 8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_CID, field_flags);
#endif

    //fs16SrcInfo1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 18, 18*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_FS_1, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LOGIC_SRC_PORT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 18, 18*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_FS_1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PORT, field_flags);

    //fs16DestMapL
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 19, 19*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 4, 4*4, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_DESTMAP, field_flags);

    //fs16NextHopInfoL
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 20, 20*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 7, 7*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_NH_OFFSET, field_flags);

    //fs2NextHopExtAndDiscardEn
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 10, 10*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_NH_EXT, field_flags);

    //fs16AuxFlexField0
    //fs16AuxFlexField1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 21, 21*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 22, 22*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_AUX_TAG_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_FLEX_HASH_CHUNK0, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 21, 21*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 22, 22*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_AUX_TAG_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_FLEX_HASH_CHUNK1, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 21, 21*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 22, 22*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_AUX_TAG_A, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_FLEX_HASH_CHUNK2, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 21, 21*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 22, 22*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_AUX_TAG_A, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_FLEX_HASH_CHUNK3, field_flags);

    //fs16VsiId
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 22, 22*16, 15);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FID, field_flags);
#if 0
    //fs16MetaData
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 23, 23*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_METADATA, field_flags);

    //fs16L2ExtField1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_L2_DATA1, field_flags);


    //fs16L2ExtField0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_L2_DATA0, field_flags);

#endif

    //CLASS A
    //fs16CategoryIdA
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PORT_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3IF_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SCL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TUNNEL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FLOW_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2+1, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 7);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FID_CID, field_flags);

    //CLASS B
    //fs16CategoryIdB
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PORT_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3IF_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SCL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TUNNEL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FLOW_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2+1, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 7);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FID_CID, field_flags);

    //CLASS C
    //fs16CategoryIdC
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PORT_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3IF_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SCL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TUNNEL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FLOW_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2+1, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 7);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FID_CID, field_flags);
    //CLASS D
    //fs16CategoryIdD
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PORT_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3IF_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SCL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TUNNEL_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 5);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FLOW_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2, 1);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 7);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 30, 30*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_CID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_FID_CID, field_flags);
  //8 ------------------------------------------

#if 0

    CBit fs8LtidInfo                      ; // 8
    CBit fs8UdfValid                      ; // 8
    CBit fs8UdfProfileId                  ; // 8
    CBit fs8LocalPhyPort                  ; // 8
    CBit fs8VrfidL                        ; // 8
    CBit fs8ExceptionId                   ; // 8
    CBit fs8AclLabel                      ; // 8
    CBit fs8TcpFlagL                      ; // 8
    CBit fs8Protocol                      ; // 8
    CBit fs8Ttl                           ; // 8
    CBit fs8Tos                           ; // 8

#endif


    //fs8Tos
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 0, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_ECN, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 2, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_DSCP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 5, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_PRECEDENCE, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 0, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_RARP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 0 + 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GARP, field_flags);
#if 0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 0, 0, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_OP_CODE, field_flags);
#endif
    //fs8Ttl
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 1, 1*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_TTL, field_flags);

    //fs8Protocol
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 2, 2*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_PROTOCOL, field_flags);

    //fs8TcpFlagL
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 3, 3*8, 6);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TCP_FLAGS, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 3, 3*8 +6, 2);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 0, 0, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TCP_ECN, field_flags);
#if 0
    //SYS_ACL_KEXT_CTRL_SEL_Y1731 = 1
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 3, 3*8, 5);
    //SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_Y1731, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_VERSION, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 3, 3*8 + 5, 3);
    //SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_Y1731, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_Y1731_OAM_LEVEL, field_flags);
#endif

    //fs8AclLabel
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 4, 4*8, 8);
    if (DRV_FROM_AT(lchip))
    {
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 32, 32*2, 1); /*fs2AclLabelHigh*/
    }
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CLASS_ID, field_flags);

    //fs8ExceptionId
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 5, 5*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_EXCEPTION_GID, field_flags);

    //fs8VrfidL
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 6, 6*8, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 5, 5*4, 4);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E2, 9, 9*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VRFID, field_flags);

    //fs8LocalPhyPort
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 7, 7*8, 8);
    if (DRV_FROM_AT(lchip))
    {
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 32, 32*2 + 1, 1); /*fs2AclLabelHigh*/
    }
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LPORT, field_flags);

    //fs8UdfAProfileId,fs2UdfAProfileIdHigh
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 8, 8*8, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 27, 27*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_PROF_ID, field_flags);

    //fs8UdfAValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 9, 9*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF1_VALID_BITMAP, field_flags);

    //fs8UdfBProfileId,fs2UdfBProfileIdHigh
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 12, 12*8, 8);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 31, 31*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_PROF_ID, field_flags);

    //fs8UdfBValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 13, 13*8, 8);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_UDF2_VALID_BITMAP, field_flags);

    //fs8LtidInfo

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 10, 10*8, 5);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_LTID0, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LT_ID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 10, 10*8, 5);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_LTID1, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LT_ID1, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 10, 10*8, 5);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_LTID2, 0);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LT_ID2, field_flags);



    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 11, 11*8+5, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LT_CLASS, field_flags);

    /*fs8LengthError*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E8, 21, 21*8, 7);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LEN_ERROR, field_flags);
    
  // -4-----------------------------------------


#if 0

    CBit fs4Reserved0                     ; // 4
    CBit fs4Ltid                          ; // 4
    CBit fs4MergeDataType                 ; // 4
    CBit fs4PortBitMapBase                ; // 4
    CBit fs4DiscardTypeL                  ; // 4
    CBit fs4InnerPriority                 ; // 4
    CBit fs4Layer4UserType                ; // 4
    CBit fs4Layer4Type                    ; // 4
    CBit fs4Layer3Type                    ; // 4
    CBit fs4CompressEtherTypeL            ; // 4
    CBit fs4VrfidM                        ; // 4
    CBit fs4DestMapH                      ; // 4
    CBit fs4FatalExceptionId              ; // 4
    CBit fs4ForwardingType                ; // 4
    CBit fs4LookupStatus                  ; // 4
    CBit fs4LookupEn                      ; // 4

#endif


    //fs4LookupEn
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 0, 0, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MACDA_LKUP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 0, 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MACSA_LKUP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 0, 2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPDA_LKUP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 0, 3, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPSA_LKUP, field_flags);

    //fs4LookupStatus
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 1, 4, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MACDA_HIT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 1, 5, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MACSA_HIT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 1, 6, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPDA_HIT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 1, 7, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IPSA_HIT, field_flags);

    //fs4ForwardingType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 2, 2*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PKT_FWD_TYPE, field_flags);

    //fs4FatalExceptionId
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 3, 3*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_EXCEPTION_FATAL_EXCP_ID, field_flags);

    //fs4DestMapH
    #if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 4, 4*4, 4);
    #endif

    //fs4VrfidM
    #if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 5, 5*4, 4);
    #endif

    //fs4CompressEtherTypeL
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 6, 6*4, 4);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 8, 8*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ETHER_TYPE, field_flags);
#if 0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 6, 6*4, 4);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 8, 8*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_RARP, field_flags);
#endif
    //fs4Layer3Type
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 7, 7*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3_TYPE, field_flags);

    //fs4Layer4Type
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 8, 8*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_TYPE, field_flags);

    //fs4Layer4UserType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 9, 9*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_USER_TYPE, field_flags);


    //fs4InnerPriority
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 10, 10*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_PRIORITY, field_flags);

    //fs4DiscardTypeL/fs2DiscardTypeH/fs2NextHopExtAndDiscardEn
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 11, 11*4, 4);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 21, 21*2, 2);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E2, 10, 10*2 + 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DISCARD, field_flags);

   //fs4PortBitMapBase
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 17, 17*16, 16);    /*fs16SrcInfo0*/
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 12, 12*4, 4);   /*fs4PortBitMapBase*/
    if (DRV_FROM_AT(lchip))
    {
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E4, 17, 17*4+2, 1);   /*fs4PortBitMapBase*/
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E2, 24, 24*2, 2);   /*fs2GportType*/
    }
    else
    {
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E2, 24, 24*2, 2);   /*fs2GportType*/
    }
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_PBM, field_flags);

   //fs4MergeDataType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 13, 13*4, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_GRE_WITH_KEY, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 13, 13*4 + 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IS_NVGRE_PKT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 13, 13*4 +2 , 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VXLAN_PKT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 13, 13*4 +3 , 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INT_PKT, field_flags);

    /*fs4L4CheckError*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 19, 19*4, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L4_HDR_ERROR, field_flags);

    /*dsIpDaSelfDefType*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 15, 15*4 , 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ROUTE_DATA, field_flags);

    /*bfdMyDiscriminator*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 29, 29*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 30, 30*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_BFD_MY_DISC, field_flags);
    /*bfdYouyDiscriminator*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 11, 11*16, 16);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E16, 12, 12*16, 16);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_BFD_YOUR_DISC, field_flags);
#if 0
    //fs4Ltid                          ; // 4  14 new
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 14, 14*4, 4);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_LT_ID, field_flags);
    #endif

  // -2-----------------------------------------

#if 0
    CBit fsCflexInfo                      ; // 2
    CBit fsL2ExtType                      ; // 2
    CBit fs2GportType                     ; // 2
    CBit fs2SymmetricSessionEn            ; // 2
    CBit fs2IpMoreAndDonotFrag            ; // 2
    CBit fs2DiscardTypeH                  ; // 2
    CBit fs2L2Type                        ; // 2
    CBit fs2Color                         ; // 2
    CBit fs2SecurityInfo                  ; // 2
    CBit fs2ElephantAndLogValid           ; // 2
    CBit fs2IsDecapAndCwValid             ; // 2
    CBit fs2RoutePktAndHitRouteMac        ; // 2
    CBit fs2IpOptionAndHeaderErr          ; // 2
    CBit fs2IpFragmentInfo                ; // 2
    CBit fs2McRpfChkFail                  ; // 2
    CBit fs2RalGalValid                   ; // 2
    CBit fs2NextHopExtAndDiscardEn        ; // 2
    CBit fs2VrfidH                        ; // 2
    CBit fs2CompressEtherTypeH            ; // 2
    CBit fs2NextHopInfoH                  ; // 2
    CBit fs2VlanNum                       ; // 2
    CBit fs2DestTypeIsEcmpOrAps           ; // 2
    CBit fs2StpState                      ; // 2
    CBit fs2ExcpValidStatus               ; // 2
    CBit fs2PiVtagValid                   ; // 2
    CBit fs2PrVtagValid                   ; // 2
    CBit fs2TcpFlagH                      ; // 2


#endif
    //fs2TcpFlagH
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 0, 0+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MIRROR_PKT, field_flags);

    //fs2PrVtagValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 1, 1*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CTAG_VALID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 1, 1*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STAG_VALID, field_flags);

    //fs2PiVtagValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 2, 2*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_CTAG_VALID, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 2, 2*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAPPED_STAG_VALID, field_flags);

    //fs2ExcpValidStatus
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 3, 3*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_EXCEPTION_EXCP_EN, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 3, 3*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_EXCEPTION_FATAL_EN, field_flags);

    //fs2StpState
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 4, 4*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STP_STATE, field_flags);

    //fs2DestTypeIsEcmpOrAps
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 5, 5*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_DEST_ECMP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 5, 5*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_DEST_APS, field_flags);

    //fs2VlanNum 6
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 6, 6*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_NUM, field_flags);

    //fs2NextHopInfoH 7
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 7, 7*2, 2);
#endif
    //fs2CompressEtherTypeH 8
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 8, 8*2, 2);
#endif

    //fs2VrfidH 9
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E2, 9, 9*2, 2);
#endif

    //fs2NextHopExtAndDiscardEn
#if 0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 10, 10*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DST_NHID, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 10, 10*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DISCARD, field_flags);
#endif
    //fs2RalGalValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 11, 11*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_GAL_EXIST, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 11, 11*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_RAL_EXIST, field_flags);

    //fs2McRpfChkFailAndGratuitousArp

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 12, 12*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MCAST_RPF_CHECK_FAIL, field_flags);

    //fs2IpFragmentInfo
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 13, 13*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_FRAG, field_flags);
    //fs2IpMoreAndDonotFrag
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 22, 22*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_IS_FRAG, field_flags);

#if 0
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 13, 13*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_FRAG, field_flags);
#endif
    //fs2IpOptionAndHeaderErr
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 14, 14*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_OPTIONS, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 14, 14*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IP_HDR_ERROR, field_flags);


    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 14, 14*2, 2);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 13, 13*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LABEL_NUM, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 13, 13*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_MAC_DA_CHK_FAIL, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 13, 13*2 + 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db,  CTC_FIELD_KEY_ARP_TARGETIP_CHK_FAIL, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 14, 14*2,  1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_MAC_SA_CHK_FAIL, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 14, 14*2 + 1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ARP_SENDERIP_CHK_FAIL, field_flags);

    //fs2RoutePktAndHitRouteMac
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 15, 15*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ROUTED_PKT, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 15, 15*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IS_ROUTER_MAC, field_flags);

    //fs2IsDecapAndCwValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 16, 16*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_DECAP, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 16, 16*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CW_EXIST, field_flags);

    //fs2ElephantAndLogValid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 17, 17*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IS_LOG_PKT, field_flags);
    
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 17, 17*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_ELEPHANT_PKT, field_flags);

    /* only egrss, Share with ELEPHANT_PKT*/
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 17, 17*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_TO_STK, field_flags);

    //fs2SecurityInfo
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 18, 18*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L2_STATION_MOVE, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 18, 18*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MAC_SECURITY_DISCARD, field_flags);

    //fs2Color
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 19, 19*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_COLOR, field_flags);

    //fs2L2Type
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 20, 20*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L2_TYPE, field_flags);

    //fs2DiscardTypeH
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 21, 21*2, 2);
#endif

    //fs2IpMoreAndDonotFrag
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 22, 22*2, 2);
#endif

    //fs2SymmetricSessionEn
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 23, 23*2, 2);
#endif

    //fsL2ExtType
#if 0
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E2, 25, 25*2, 2);
#endif


    //fsCflexInfo
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 26, 26*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_LKUP, field_flags);
    //fsCflexInfo
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 26, 26*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_STK_HDR_EXIST, field_flags);

    //fs32UdfA2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 16, 16*32+26, 5);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_A, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_HDR_BMP, field_flags);

    //fs32UdfB2
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 32, 32*32+26, 5);
    SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_UDF_B, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_STK_HDR_BMP, field_flags);

    //fsL3ExtType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 28, 28*2, 2);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_L3_EXT_TYPE, field_flags);

    //fs2IsLocalSid
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 29, 29*2+1, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INNER_HEAD, field_flags);

    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 29, 29*2, 1);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_IS_MY_SID, field_flags);

#if 0
    mergeDataShareValid = IngAclInputBus.aclKeyMergeInnerAndOuterHdr &&
                      DsLtidSelectAd.fsMergeDataShareValid &&
                      ((isVxlan & ProgramTcamAclCtl.fsMergeDataShareTypeCtl(0))
                      || (isGreNoKey & ProgramTcamAclCtl.fsMergeDataShareTypeCtl(1))
                      || (isGreWithKey & ProgramTcamAclCtl.fsMergeDataShareTypeCtl(2)));
    mergeDataShareType(1,0) = CBit(2, 'b', "00", 2);
    if(mergeDataShareValid)
    {
        if(isVxlan)
        {
            mergeDataShareType(1,0) = CBit(2, 'b', "01", 2);
        }
        else if(isGreNoKey)
        {
            mergeDataShareType(1,0) = CBit(2, 'b', "10", 2);
        }
        else if(isGreWithKey)
        {
            mergeDataShareType(1,0) = CBit(2, 'b', "11", 2);
        }

    }

    if(mergeDataShareType(1,0) != CBit(2, 'b', "00", 2))
    {
        ProgramAcl16bBus.fs16PrInnerVtag(15,0) = (mergeDataShareType(1,0),IngAclPktDecodeBus.aclUseMergeData(61,48));
        if(ProgramTcamAclCtl.fsMergeDataShareTypeCtl(3))
        {
            (ProgramAcl32bBus.fs32DMac(31,0),ProgramAcl16bBus.fs16DMac(15,0)) = IngAclPktDecodeBus.aclUseMergeData(47,0);
        }
        else
        {
            (ProgramAcl32bBus.fs32SMac(31,0),ProgramAcl16bBus.fs16SMac(15,0)) = IngAclPktDecodeBus.aclUseMergeData(47,0);
        }
    }

    //fs32MergeData0, fs4MergeDataType
    SYS_ACL_KFIELD_CFG_INIT(lchip);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 15, 15*32, 32);
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E4, 13, 13*4, 3);
    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_AWARE_TUNNEL_INFO, field_flags);
#endif

    //fs2McRpfChkFail
    //CTC_FIELD_KEY_AWARE_TUNNEL_INFO use mac sa
    SYS_ACL_KFIELD_CFG_INIT(lchip);

    SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 1, 1*16, 16); /*fs16SMac(15,0)*/
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 1, 1*32, 32); /*fs32SMac(31,0)*/
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E16, 3, 3*16, 16); /*fs16PrInnerVtag*/
    SYS_ACL_KFIELD_CFG_OFFSET_ADD(3, SYS_ACL_KEXT_SECTION_L1E2, 12, 12*2+1, 1); /*fs2McRpfChkFail*/

    SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_AWARE_TUNNEL_INFO, field_flags);


    if (DRV_FROM_AT(lchip))
    {
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32 + 28, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_CBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32 + 29, 1);    /*fs32NshHeaderData0*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_OBIT, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 44, 44*32, 8);         /*fs32NshHeaderData0*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_NEXT_PROTOCOL, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32 + 8, 24);    /*fs32NshHeaderData1*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_SPI, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 43, 43*32, 8);         /*fs32NshHeaderData1*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_SI, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 33, 33*2, 1);           /*fs2NshInfo*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_TERMINAL, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 33, 33*2 + 1, 1);       /*fs2NshInfo*/
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_INNER_IS_RTMAC, field_flags);

        /*class A*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 3);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NEXTHOP_CID, field_flags);

        /*class B*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 3);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NEXTHOP_CID, field_flags);

        /*class C*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 3);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NEXTHOP_CID, field_flags);

        /*class D*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 3);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NEXTHOP_CID, field_flags);

        /*fs32MplsControlWord*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 29, 29*32, 16);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SRC_GPORT, field_flags);

        /*fs2RalGalValid*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 11, 11*2 + 1, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_VLAN_XLATE0_HIT, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 11, 11*2, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, SYS_ACL_FIELD_VLAN_XLATE1_HIT, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 11, 11*2, 2);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_VLAN_XLATE_HIT, field_flags);

        /*fs4ingPktInfo*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 17, 17*4, 2);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_SNIFFING_PKT, field_flags);

        /*fs2McRpfChkFail*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 12, 12*2, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MARK_ECN, field_flags);
        /*fs4TunnelType*/
        //SYS_ACL_KFIELD_CFG_INIT(lchip);
        //SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 18, 18*4, 1);
        //SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_MARK_ECN, field_flags);
        /*fs4TunnelType*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 18, 18*4+1, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_CONGEST_EVENT, field_flags);
        /*fs4TunnelType*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E4, 18, 18*4+2, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_BURST_EVENT, field_flags);

        /*fs16Reserved*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 38, 38*16, 16);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LOGIC_DST_PORT, field_flags);

        /*l3IfTypeEncode*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 35, 35*2, 2);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NAT_IFTYPE, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 28, 28*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_A, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LDP_CID, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 27, 27*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_B, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LDP_CID, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 26, 26*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_C, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LDP_CID, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E16, 25, 25*16, 16);
        SYS_ACL_KFIELD_CFG_CTRL_SEL_ADD(SYS_ACL_KEXT_CTRL_SEL_CLASSID_D, 5);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_LDP_CID, field_flags);

        /*fs4ingPktInfo*/
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E2, 36, 36*2, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_APS_PROTECT1_EN, field_flags);

    }
    else
    {
        /*NSH*/
        //fs32DIp0 fs32SIp0
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_NEXT_PROTOCOL, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 28, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_CBIT, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 2, 2*32 + 29, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_OBIT, field_flags);

        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32, 8);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_SI, field_flags);
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 6, 6*32 + 8, 24);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NSH_SPI, field_flags);

        //fs4DestMapH,fs32MplsInbandOamFIH
        SYS_ACL_KFIELD_CFG_INIT(lchip);

        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 34, 34*32, 8);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(1, SYS_ACL_KEXT_SECTION_L1E32, 34, 34*32 + 12, 20);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(2, SYS_ACL_KEXT_SECTION_L1E4, 4, 4*4 + 3, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_FLOW_ID, field_flags);

        //fs32MplsInbandOamFIH.LFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 34, 34*32+11, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_L_FLAG, field_flags);

        //fs32MplsInbandOamFIH.DFlag
        SYS_ACL_KFIELD_CFG_INIT(lchip);
        SYS_ACL_KFIELD_CFG_OFFSET_ADD(0, SYS_ACL_KEXT_SECTION_L1E32, 34, 34*32+10, 1);
        SYS_ACL_KFIELD_CFG_INSERT(lchip, db, CTC_FIELD_KEY_NPM_IM_D_FLAG, field_flags);
    }

exit:
    STS_ACL_FUNC_EXIT();
}


STATIC int32
_sys_tmm_acl_ingress_ext_cfg_db_init(uint8 lchip)
{
    int32 idx = 0;                     /* Index iterator.                     */
    int32 level = 0;                   /* Extractor hierarchy level.          */
    int32 gran = 0;                    /* Extractor granularity.              */
    int32 ext_num = 0;                 /* Extractor number.                   */
    int32 part;                        /* Entry part number.                  */
    uint32 base = 0;
    sys_acl_kext_attrs_t ext_attrs;
    sys_acl_kext_attrs_t temp_attrs;
    sys_acl_kext_attrs_t *attrs = &temp_attrs;
    uint32 ext_attrs_size = 0;
    SYS_ACL_KEXT_CFG_DECL;              /* Extractors config declaration.      */
    sys_acl_kext_cfg_db_t *ext_cfg_db = NULL;

    STS_ACL_FUNC_ENTER(lchip);

    ext_attrs_size = sizeof(sys_acl_kext_attrs_t);
    sal_memset(attrs, 0, ext_attrs_size);

    SYS_ACL_ALLOC(ext_cfg_db,
                sizeof(sys_acl_kext_cfg_db_t));
    p_usw_acl_master[lchip]->kgn_ext_cfg_db_arr[SYS_ACL_KEYGEN_MODE_SINGLE] = ext_cfg_db;

    part = 0;


    /* LV1 32-bit extractor(4) section. */
    level = 1;
    gran = 32;
    ext_num = SYS_ACL_EXT_L1_E32_MAX;
    base = 0;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2S1,
                   base + idx*gran, attrs);
    }


    /* LV1 16-bit extractors(10) section. */

    base =  base + ext_num*gran; /*[287:128]*/
    level = 1;
    gran = 16;
    ext_num = SYS_ACL_EXT_L1_E16_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2S1,
                   base + idx*gran, attrs);
    }


    /* LV1 8-bit extractors(8) section. */
    base = 0;  /*[63:0]*/
    level = 1;
    gran = 8;
    ext_num = SYS_ACL_EXT_L1_E8_MAX - 1;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2S2,
                                 base + idx*gran, attrs);
    }



    /* LV1 4-bit extractors(10) section. */
    base = base + SYS_ACL_EXT_L1_E8_MAX*gran; /*[103:64]*/
    level = 1;
    gran = 4;
    ext_num = SYS_ACL_EXT_L1_E4_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2S2,
                                 base + idx*gran, attrs);
    }


    /* LV1 2-bit extractors(8) section. */
    base = base + ext_num*gran; /*[159:104]*/
    level = 1;
    gran = 2;
    ext_num = SYS_ACL_EXT_L1_E2_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2S2,
                                 base + idx*gran, attrs);
    }


    /* LV2 16-bit extractors(10) section. */
    base =  0;
    level = 2;
    gran = 16;

    ext_num = 4;
    /*Bits[63:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L2S1, SYS_ACL_KEXT_SECTION_L3S1,
                                 base + idx*gran, attrs);
    }


    ext_num = 6;
    /*Bits[95:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx + 4,
                                 SYS_ACL_KEXT_SECTION_L2S1, SYS_ACL_KEXT_SECTION_L3S2,
                                 base + idx*gran, attrs);
    }

    /* LV2 8-bit extractors(8) section. */
    base =  base + ext_num*gran; /*96*/
    level = 2;
    gran = 8;
    ext_num = 8;
    /*Bits[159:96]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L2S2, SYS_ACL_KEXT_SECTION_L3S2,
                                 base + idx*gran, &ext_attrs);
    }


    /* LV2 4-bit extractors(10) section. */
    base =  base + ext_num*gran; /*160*/
    level = 2;
    gran = 4;
    ext_num = 10;
    /*Bits[199:160]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L2S2, SYS_ACL_KEXT_SECTION_L3S2,
                                 base + idx*gran, &ext_attrs);
    }


    /* Initialize Level2 2-bit extractors(8) section. */
    base =  base + ext_num*gran; /*200*/
    level = 2;
    gran = 2;
    ext_num = 8;
    /*Bits[215:200]*/

    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L2S2, SYS_ACL_KEXT_SECTION_L3S2,
                                 base + idx*gran, &ext_attrs);
    }

    // ==================== level 3 ===========================================

    /* LV3 16-bit extractors(0) section. */
    base = 0;
    level = 3;
    gran = 16;
    ext_num = 4;


    /*Bits[63:0]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);


    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L3S1, SYS_ACL_KEXT_SECTION_FK,
                                 base + idx*gran, &ext_attrs);
    }


    /* Initialize four Level_3 4-bit extractors(21) section. */
    base =  base + ext_num*gran; /*64*/
    level = 3;
    gran = 4;
    ext_num = SYS_ACL_EXT_L3_E4_MAX - 1;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3S2, SYS_ACL_KEXT_SECTION_FK,
                   base + idx* gran , attrs);
    }



    /* Initialize 5 Level_3 2-bit extractors(5) section. */
    base =  base + SYS_ACL_EXT_L3_E4_MAX*gran; /*148*/
    level = 3;
    gran = 2;
    ext_num = SYS_ACL_EXT_L3_E2_MAX;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L3S2, SYS_ACL_KEXT_SECTION_FK,
                                 base  + idx * gran, attrs);
    }


    /* Initialize 2 Level_3 1-bit extractors(2) section. */
    base =  base + ext_num*gran; /*158*/
    level = 3;
    gran = 1;
    ext_num = SYS_ACL_EXT_L3_E1_MAX - 1;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L3S2, SYS_ACL_KEXT_SECTION_FK,
                                 base  + idx * gran, attrs);
    }

    /* Initialize Level_4 extractor section. */
    level = 4;
    gran = 160;
    EXT_DB_ADD(lchip, ext_cfg_db, part, level, gran, 0,
                             SYS_ACL_KEXT_SECTION_FK, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);



    // =================================================================================
    //                                    320
    // =============================================================================

    /* 320 bits mode - Initialize Level_1 32-bit extractor section. */
    ext_cfg_db = NULL;
    SYS_ACL_ALLOC(ext_cfg_db,
                sizeof(sys_acl_kext_cfg_db_t));
    p_usw_acl_master[lchip]->kgn_ext_cfg_db_arr[SYS_ACL_KEYGEN_MODE_DOUBLE] = ext_cfg_db;


    /* LV1 32-bit extractor(4) section. */
    level = 1;
    gran = 32;
    ext_num = SYS_ACL_EXT_L1_E32_MAX;
    base = 0;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2AS1,
                   base + idx*gran, attrs);

        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2BS1,
                   base + idx*gran, attrs);

    }


    /* LV1 16-bit extractors(10) section. */

    base =  base + ext_num*gran; /*[287:128]*/
    level = 1;
    gran = 16;
    ext_num = SYS_ACL_EXT_L1_E16_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2AS1,
                   base + idx*gran, attrs);

        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2BS1,
                   base + idx*gran, attrs);

    }


    /* LV1 8-bit extractors(8) section. */
    base = 0;  /*[63:0]*/
    level = 1;
    gran = 8;
    ext_num = SYS_ACL_EXT_L1_E8_MAX - 1;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2AS2,
                   base + idx*gran, attrs);

        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2BS2,
                   base + idx*gran, attrs);
    }



    /* LV1 4-bit extractors(10) section. */
    base = base + SYS_ACL_EXT_L1_E8_MAX*gran; /*[103:64]*/
    level = 1;
    gran = 4;
    ext_num = SYS_ACL_EXT_L1_E4_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2BS2,
                   base + idx*gran, attrs);
    }


    /* LV1 2-bit extractors(8) section. */
    base = base + ext_num*gran; /*[159:104]*/
    level = 1;
    gran = 2;
    ext_num = SYS_ACL_EXT_L1_E2_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2AS2,
                                 base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                                 SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2BS2,
                                 base + idx*gran, attrs);
    }


    /* LV2 16-bit extractors(10) section. */
    base =  0;
    level = 2;
    gran = 16;

    ext_num = 4;
    /*Bits[63:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS1, SYS_ACL_KEXT_SECTION_L3AS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS1, SYS_ACL_KEXT_SECTION_L3BS1,
                   base + idx*gran, attrs);
    }


    ext_num = 6;
    /*Bits[95:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx + 4,
                   SYS_ACL_KEXT_SECTION_L2AS1, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx + 4,
                   SYS_ACL_KEXT_SECTION_L2BS1, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, attrs);
    }

    /* LV2 8-bit extractors(8) section. */
    base =  base + ext_num*gran; /*96*/
    level = 2;
    gran = 8;
    ext_num = 8;
    /*Bits[159:96]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
    }


    /* LV2 4-bit extractors(10) section. */
    base =  base + ext_num*gran; /*160*/
    level = 2;
    gran = 4;
    ext_num = 10;
    /*Bits[199:160]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
    }


    /* Initialize Level2 2-bit extractors(8) section. */
    base =  base + ext_num*gran; /*200*/
    level = 2;
    gran = 2;
    ext_num = 8;
    /*Bits[215:200]*/

    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
    }

    // ==================== level 3 ===========================================

    /* LV3 16-bit extractors(0) section. */
    base = 0;
    level = 3;
    gran = 16;
    ext_num = 4;


    /*Bits[63:0]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);


    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS1, SYS_ACL_KEXT_SECTION_FKA,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS1, SYS_ACL_KEXT_SECTION_FKB,
                   base + idx*gran, &ext_attrs);
    }


    /* Initialize four Level_3 4-bit extractors(21) section. */
    base =  base + ext_num*gran; /*64*/
    level = 3;
    gran = 4;
    ext_num = SYS_ACL_EXT_L3_E4_MAX - 1;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base + gran * idx , attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base + gran * idx , attrs);
    }



    /* Initialize 5 Level_3 2-bit extractors section. */
    base =  base + SYS_ACL_EXT_L3_E4_MAX*gran; /*148*/
    level = 3;
    gran = 2;
    ext_num = SYS_ACL_EXT_L3_E2_MAX;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base  + idx * gran, attrs);
    }


    /* Initialize 2 Level_3 1-bit extractors section. */
    base =  base + ext_num*gran; /*158*/
    level = 3;
    gran = 1;
    ext_num = SYS_ACL_EXT_L3_E1_MAX - 1;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base  + idx * gran, attrs);
    }

    /* Initialize Level_4 extractor section. */
    level = 4;
    gran = 160;
    EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FK, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);
    EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FKA, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);
    EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FKB, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);



   /*
     **************************************************************
                     480
     ***************************************************************
   */

    /* 480 bit mode - Initialize Level_1 32-bit extractor section. */
    ext_cfg_db = NULL;
    SYS_ACL_ALLOC(ext_cfg_db,
                sizeof(sys_acl_kext_cfg_db_t));
    p_usw_acl_master[lchip]->kgn_ext_cfg_db_arr[SYS_ACL_KEYGEN_MODE_TRIPLE] = ext_cfg_db;


    /* LV1 32-bit extractor(4) section. */
    level = 1;
    gran = 32;
    ext_num = SYS_ACL_EXT_L1_E32_MAX;
    base = 0;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2AS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2BS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E32, SYS_ACL_KEXT_SECTION_L2CS1,
                   base + idx*gran, attrs);
    }


    /* LV1 16-bit extractors(10) section. */

    base =  base + ext_num*gran; /*[287:128]*/
    level = 1;
    gran = 16;
    ext_num = SYS_ACL_EXT_L1_E16_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2AS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2BS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E16, SYS_ACL_KEXT_SECTION_L2CS1,
                   base + idx*gran, attrs);
    }


    /* LV1 8-bit extractors(8) section. */
    base = 0;  /*[63:0]*/
    level = 1;
    gran = 8;
    ext_num = SYS_ACL_EXT_L1_E8_MAX - 1;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2BS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E8, SYS_ACL_KEXT_SECTION_L2CS2,
                   base + idx*gran, attrs);
    }



    /* LV1 4-bit extractors(10) section. */
    base = base + SYS_ACL_EXT_L1_E8_MAX*gran; /*[103:64]*/
    level = 1;
    gran = 4;
    ext_num = SYS_ACL_EXT_L1_E4_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2BS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E4, SYS_ACL_KEXT_SECTION_L2CS2,
                   base + idx*gran, attrs);
    }


    /* LV1 2-bit extractors(8) section. */
    base = base + ext_num*gran; /*[159:104]*/
    level = 1;
    gran = 2;
    ext_num = SYS_ACL_EXT_L1_E2_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2BS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L1E2, SYS_ACL_KEXT_SECTION_L2CS2,
                   base + idx*gran, attrs);
    }


    /* LV2 16-bit extractors(10) section. */
    base =  0;
    level = 2;
    gran = 16;

    ext_num = 4;
    /*Bits[63:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS1, SYS_ACL_KEXT_SECTION_L3AS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS1, SYS_ACL_KEXT_SECTION_L3BS1,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2CS1, SYS_ACL_KEXT_SECTION_L3CS1,
                   base + idx*gran, attrs);
    }


    ext_num = 6;
    /*Bits[95:0]*/
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx + 4,
                   SYS_ACL_KEXT_SECTION_L2AS1, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx + 4,
                   SYS_ACL_KEXT_SECTION_L2BS1, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx + 4,
                   SYS_ACL_KEXT_SECTION_L2CS1, SYS_ACL_KEXT_SECTION_L3CS2,
                   base + idx*gran, attrs);
    }

    /* LV2 8-bit extractors(8) section. */
    base =  base + ext_num*gran; /*96*/
    level = 2;
    gran = 8;
    ext_num = 8;
    /*Bits[159:96]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2CS2, SYS_ACL_KEXT_SECTION_L3CS2,
                   base + idx*gran, &ext_attrs);
    }


    /* LV2 4-bit extractors(10) section. */
    base =  base + ext_num*gran; /*160*/
    level = 2;
    gran = 4;
    ext_num = 10;
    /*Bits[199:160]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2CS2, SYS_ACL_KEXT_SECTION_L3CS2,
                   base + idx*gran, &ext_attrs);
    }


    /* Initialize Level2 2-bit extractors(8) section. */
    base =  base + ext_num*gran; /*200*/
    level = 2;
    gran = 2;
    ext_num = 8;
    /*Bits[215:200]*/

    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2AS2, SYS_ACL_KEXT_SECTION_L3AS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2BS2, SYS_ACL_KEXT_SECTION_L3BS2,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L2CS2, SYS_ACL_KEXT_SECTION_L3CS2,
                   base + idx*gran, &ext_attrs);
    }

    // ==================== level 3 ===========================================

    /* LV3 16-bit extractors(0) section. */
    base = 0;
    level = 3;
    gran = 16;
    ext_num = 4;

    /*Bits[63:0]*/
    sal_memset(&ext_attrs, 0, ext_attrs_size);
    CTC_BMP_SET(ext_attrs.w, SYS_ACL_KEXT_ATTR_PASS_THRU);

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS1, SYS_ACL_KEXT_SECTION_FKA,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS1, SYS_ACL_KEXT_SECTION_FKB,
                   base + idx*gran, &ext_attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3CS1, SYS_ACL_KEXT_SECTION_FKC,
                   base + idx*gran, &ext_attrs);
    }


    /* Initialize four Level_3 4-bit extractors(21) section. */
    base =  base + ext_num*gran; /*64*/
    level = 3;
    gran = 4;
    ext_num = SYS_ACL_EXT_L3_E4_MAX - 1;
    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base + gran * idx , attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base + gran * idx , attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3CS2, SYS_ACL_KEXT_SECTION_FKC,
                   base + gran * idx , attrs);
    }



    /* Initialize 5 Level_3 2-bit extractors section. */
    base =  base + SYS_ACL_EXT_L3_E4_MAX*gran; /*148*/
    level = 3;
    gran = 2;
    ext_num = SYS_ACL_EXT_L3_E2_MAX;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3CS2, SYS_ACL_KEXT_SECTION_FKC,
                   base  + idx * gran, attrs);
    }


    /* Initialize 2 Level_3 1-bit extractors section. */
    base =  base + ext_num*gran; /*158*/
    level = 3;
    gran = 1;
    ext_num = SYS_ACL_EXT_L3_E1_MAX - 1;

    for (idx = 0; idx < ext_num; idx++)
    {
        EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3AS2, SYS_ACL_KEXT_SECTION_FKA,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3BS2, SYS_ACL_KEXT_SECTION_FKB,
                   base  + idx * gran, attrs);
        EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, idx,
                   SYS_ACL_KEXT_SECTION_L3CS2, SYS_ACL_KEXT_SECTION_FKC,
                   base  + idx * gran, attrs);
    }

    /* Initialize Level_4 extractor section. */
    level = 4;
    gran = 160;
    EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FK, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);
    EXT_DB_ADD(lchip, ext_cfg_db, 0, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FKA, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);
    EXT_DB_ADD(lchip, ext_cfg_db, 1, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FKB, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);
    EXT_DB_ADD(lchip, ext_cfg_db, 2, level, gran, 0,
               SYS_ACL_KEXT_SECTION_FKC, SYS_ACL_KEXT_SECTION_DISABLE, 0, attrs);

exit:
    STS_ACL_FUNC_EXIT();
}

int32
sys_tmm_acl_extract_db_init(uint8 lchip)
{
    _sys_tmm_acl_ingress_ext_cfg_db_init(lchip);
    _sys_tmm_acl_ingress_field_cfg_db_init(lchip);

    return 0;
}

void
sys_tmm_acl_extract_db_deinit(uint8 lchip)
{
    uint16  loop = 0;
    uint16  loop2 = 0;
    sys_acl_kfield_cfg_info_db_t *kgn_field_cfg_info_db;
    sys_acl_kext_cfg_db_t *kgn_ext_cfg_db;

    for (loop=0; loop<SYS_ACL_KEYGEN_MODE_COUNT; loop++)
    {
        kgn_ext_cfg_db = p_usw_acl_master[lchip]->kgn_ext_cfg_db_arr[loop];
        if (!kgn_ext_cfg_db)
        {
            continue;
        }
        for (loop2 = 0; loop2 < SYS_ACL_KEXT_LEVEL_COUNT; loop2++)
        {
            mem_free(kgn_ext_cfg_db->ext_cfg[loop2]);
        }
        for (loop2 = 0; loop2 < SYS_ACL_KEXT_SECTION_COUNT; loop2++)
        {
            mem_free(kgn_ext_cfg_db->sec_cfg[loop2]);
        }
        mem_free(kgn_ext_cfg_db);
    }
    kgn_field_cfg_info_db = p_usw_acl_master[lchip]->kgn_field_cfg_info_db;
    if (kgn_field_cfg_info_db)
    {
        for (loop = 0; loop < SYS_ACL_FIELD_COUNT; loop++)
        {
            if (!kgn_field_cfg_info_db->field_cfg_info[loop])
            {
                continue;
            }
            mem_free(kgn_field_cfg_info_db->field_cfg_info[loop]->field_cfg_arr);
            mem_free(kgn_field_cfg_info_db->field_cfg_info[loop]);
        }
        mem_free(kgn_field_cfg_info_db);
    }
}

#endif

